Design Of Low Power Pipelined Adc For Motion-detection Cmos Image Sensor

In the mixed-signal system, ADCs is responsible for converting the analog signal into digital signal.As the number of integrated circuits increased, its application fields also expanded. Because of its high-speed,high precision and low-power consumption, pipelined ADC was widely applied. This paper used to research the monitor area of the CMOS image sensor and designed a 5M,10-bit precision pipeline ADC which based on theory of motion detection.The design is based on SMIC 0.18μm CMOS process.Pipelined ADC is composed of SHA and nine MDAC circuits.The MDAC circuit used the traditional structure of 1.5 bit per stage.Before the design,a system model is build up by Matlab Simulink in which we consider the impact of non-ideal factors on the system precision, such as KTC noise , OTA gain error, the error of comparator and so on.Then through the corresponding simulation,the values of the sample capacitors, OTA gain and other design specifications were determined.This thesis focused on the achievment of low-power pipeline ADC under motion detection structrue,this was accomplished by the system architecture and circuit structure: In the system architecture, the pipelined ADC worked under the"on"mode or"off"mode, the simulation showed that the power under"off"down mode is only 32% of that under"on"mode; In the circuit structure,telescopic cascode op amp was used as the main amplifier per stage to consume less power; The capacitors of first few levels were scaled to reduce requirements of operational amplifier bandwidth and thereby reduce power consumption;The use of dynamic comparator which don't consume static power consumption also make the power consumption down;The sample capacitance of each stage and the op amp operating current were optimized after comprehensive consideration between system power requirements and noise.After the system simulation of the designed pipeline ADC,the ENOB is 9.9 bit when the input signal for test is 1/50 of the sample rate.The power consumption under"on"mode is 1.83mW. The layout of the ADC is calfully designed.