Low Power Design In 10 Bit CMOS Pipliened ADC

With the development of IC design and process,the integrated circuit have enter into the system-on-chip (SOC) stage. In the communications, video processing, and other mixed-signal system, the high-speed, low-power ADC is a very crucial part. Compared with other structures, pipeline ADC structure can achieve both high-speed and very high resolutions. In this paper,a 10 bit 40 M pipelined ADC was designed in SMIC 0.18 urn process.The first chapter of this article made systematic introduction of ADC, then discussed the design methodology and criteria on low-power dissipation high-speed pipelined ADC through theoretical analysis of power restrain of ADC. We will present the design consideration from architecture to circuit. 1.we put the emphasis on SHA-less front end structure, 2. optimized resolution per stages and stage scaling.3. In circuit level, the power optimization was performed for the core modules of operational amplifier and quantizer.Using SMIC (SMIC) 0.18μm 1P6M CMOS PDK as the post-simulation model, The test result reveals that the ADC designed with this method achieves the 8.7 bit at full speed of 40MHz when input frequency is 9 MHz.The power is 48 mw.