Ldpc Encoding Algorithm And Hardware Implement

The business need of communication systems is increasing continuously, so error-correction coding techniques have attracted a lot of attention. This thesis focuses on achieving the reliability and effectiveness of information transmission at low signal noise ratio (SNR). Based on this background, the thesis here uses the method of Low-Density Parity-Code (LDPC) and continuous phase modulation (Minimum Shift Keying). Communication system requires that the information can be transmitted reliability in the condition of low SNR, at the same time, the length of the LDPC code is smaller and the code-rate is higher. This thesis mainly researches on the encoding algorithms of the LDPC code and the structure of the check matrix, which can be achieved through Field Programmable Gate Array (FPGA).In order to implement the LDPC encoder based on FPGA, many factors influencing properties of encoder have been studied here, such as construction of check matrix, code length, and code rate etc. And a comparison has been done based on simulation. The thesis studies on the structure algorithms of the check matrix of the LDPC code, including the random algorithms of Gallager, Mackay, PEG and the algebraic algorithm that are based on the cyclic shift matrix. Then the encoding algorithms based on check matrix and generator matrix were researched and the occupation of the resources and encoding complexity were analyzed. Finally, the thesis has used under-triangle algorithm and serial quasi-cyclic algorithm.Top-level circuit and basic function partition of the LDPC encoder is given and designed by Verilog HDL language. And a validation has been done through ISE comprehension, layout, and timing simulation on Modelsim SE 6.2b. Then the LDPC encoder has implemented on FPGA. Through the comparison of two encoders'encoding rate and occupation of the resources, the serial quasi-cyclic encoder has been selected.At last, a message sequence is sent from the computer serial port to the development board. The code received is been tested, from the result we can see the encoder can work well. Then, the whole test system is realized by Visual C Plus Plus Information resource, channel and bit error rate statistics are realized by Visual C Plus Plus. LDPC encoder, LDPC decoder, modulation and demodulation of Minimum Shift Keying are implementation based on FPGA. This thesis provided the whole test scheme and result. The test results indicate that LDPC encoder performance based on FPGA is basically same as the theoretical coding performance, and the design of the encoder is correct.