Code Construction And Encoder Implementation Of High Payload Low Density Parity Check Code

LDPC codes perform close to the Shannon limit. It has been widely adopted by standards in the field of wireless communication, including DVB-TH, DVB-S2, IEEE 802.11n and IEEE 802.16e. LDPC codes have become one of the key technologies in 3G and even the next generation communication network.Today, there are two popular ways of constructing LDPC codes, namely Single Expansion code construction and Repeat Accumulate like code construction, both of which take advantage of the Quasi Cyclic structure. Corresponding to the two kinds of LDPC codes, two popular encoding algorithms apply, namely algorithm based on generation matrix and algorithm based on iterative decoding. The algorithm based on generation matrix can achieve a high payload, while it consumes lots of registers and ROM. The algorithm based on iterative decoding can be easily implemented, while LDPC codes with relatively high performance are hard to construct.After a detail analysis of the above construction methods and encoding algorithms, with consideration to the codec complexity, a flexible construction method called Duplex Expansion is proposed to achieve a high payload. Taking advantage of the Quasi Cyclic structure of the sparse H matrix, a new encoder algorithm is also presented.Duplex Expansion code construction is usually realized through a Permulation Expansion on mother matrix followed by a Cyclic Shift Expansion on base matrix. For flexible code rate and code length, multiple Permulation Expansion factors (PEx) and Cyclic Shift Expansion factors (CSEx) shall be supported by codec. The features of Duplex Expansion code construction illustrated in this article lie in: fixed CSEx factor and flexible PEx factors, facilitating decoder implementation; approximate regular LDPC code, making codec complexity low; pseudo random chosen PEx factors, improving performance. Thus, this specific Duplex Expansion code construction achieves a good tradeoff between hardware complexity and performance.The new encoding algorithm has enabled resource sharing wherever possible, which makes the encoder complexity in linear proportion to the code length. Fully considering a high payload, the forward substitution in RU algorithm is removed. Meanwhile, the number of pipeline stages has been reduced from 6 to 4. In order to reduce the encoding latency, all pipelines are designed to consume approximately the same number of clocks.Compared to RU algorithm, this proposed scheme is more flexible to support multiple code rates and code lengths with much higher payload. Compared to the algorithm based on generation matrix, it consumes much lower register and ROM resources, thus achieves a higher payload per unit resource. Compared to the algorithm based on Repeat Accumulate structure and iterative decoding algorithm, it is much easier to construct the codes with high performance. All the results have been proven by Xilinx Vertex II pro 70 FPGA.Upon board level testing, results show that the above Duplex Expansion code construction and encoder design of LDPC code can achieve a high payload with rather low resources. It enjoys a fairly high merit in practical application.Nowadays, irregular, flexible and joint source-channel-modulation LDPC code design has become the focus of future research. And the construction method of joint source-channel-modulation code and its corresponding encoding algorithm will continue to be studied in detail.