Full Custom Design And Implication Of Data TLB

Translate Look-aside Buffer(TLB) accelerates the address transition rate from virtual address to physical address in processor, but the address mapping process is often on the critical path. Therefore, high-performance processor must optimize the TLB in order to reduce the address translation delay, only in this way can meet the system requirements of high-speed memory access. The main aim of this subject is to explore how to improve the speed of address translation in TLB.This thesis studies the full-custom design theory and methodology of high performance TLB. The proposed high performance TLB is optimized at algorithm level, logic level, circuit level and layout level. It is implemented in 65nm CMOS process.This thesis mainly contributes to the following three aspects:Have implemented the main modules in TLB-RAM array by full-custom designing method. We adopt 8T memory cells, which is different from 6T cells used in other storage units in X processor. Consequently, this approach not only enhances the stability but also simplifies the design of reading and writing ports; Read-out circuits are elaborately designed, which greatly shortened the time to read.The replacement strategy in TLB is realized by using pseudo LRU algorithm, and the hardware circuit is particularly designed. Two methods: adding hardware overhead and doing Boolean equipollence is used to optimize the circuit delay durning the whole process of circuit design (including a variety of control logic).CAM, RAM, and other functional modules are banded together organically as a full integrality in two aspects: circuit designing and layout drawing. And the accomplished TLB can execute matching, reading and writing operations in one single clock cycle so as to meet the meet the system design requirements.The area of ultimate layout is 0.243mm2. The simulation result of layout indicates that the delay of matching operation is 677ps, achieving the design goal.