Design And Implementation Of Expansion Bus Host Port Interface In YHFT-DSPX

YHFT-DSPX is a high-performance 32-bit fix-point programmable digital signal processor that is designed by National University of Defense Technology independently. It is widely applied to various fields such as audio, graphic and image, signal processing, communications and other fields. This article designed and implemented a 32-bit parallel Host Port interface for YHFT-DSPX, which can enhance the control of external host to the DSP and provide a quick access for achieving the data communications between DSP and external parallel devices.We made a thorough research for the functions and characteristics of the Host Port interface and extended its function. Expanded Host Port interface can operate in either asynchronous mode or synchronous mode and supports multiple interface protocols. It can be easily interfaces to a variety of general purpose processor, PCI bridge chip and the general asynchronous devices. We have accomplished the overall structure design. According to the functions of Host Port interface, we have divided it into several sub-modules and accomplished the logical design of each module. It focused on the problems of multiple clock domains in the logic design process. We have successfully resolved the problem of signal and data transmission between different clock domains by using different solutions. Through the use of Finite State Machine, We realized a flexible and efficient control of data transmission. At the same time,we completed the design of read buffer and write buffer, them provide a strong guarantee for achieving burst transfer host when Host Port interface is operating in synchronous mode.We have given a full optimization to the system of Host Port interface by some methods and made its timing closure while the area gained satisfactory results. By carrying out simulation in different design level with plenty testbench, it can be guaranteed that Host interface interface meet the functional requirements and each timing parameter satisfy the requirements when it inteface to external device.