The Design And Implementation Of Shared Memory Controller Port For Multi-core X-DSPX

With more application of the Digital Signal Processing, and greater expectationtoward the performance, power consumption and cost of the DSP system, people haveswitched their attention from mononuclear DSP to multi-core DSP technology.Meanwhile, due to the increasing number of concurrent scheduling threads, how toprovide fast shared data access for the chip computing resources has become one of thekey technology to be solved in multi-core DSP. Therefore, the research of efficientshared memory technology on condition of multi-core will play a significant role inpromoting further development of multi-core DSP technology.X-DSPX is a kind of32-bit floating-point multi-core DSP microprocessor chipswith high-performance, which was developed by our school independently. This paperwill analyze the functional features of the mainstream DSP’s shared memorycomponents in depth, according to the X-DSPX’s requirements in design, starting frommemory array, data path and controller, it designed and realized the SMC componentsabout the read/write command queue, arbitrator, command decoding, address generationand the data serial-parallel conversion, thus proposed a more effective arbitrationmechanism. The key work of the paper includes:1、The design and realization of X-DSPX’s SMC components. Based on thefunctional requirements of X-DSPX toward the SMC parts, it gained access to SMCmemory for the four DSP at the same time, in addition, through the SMC part’ access tomemory space, such as DDR2, EMIF, remote L2, it succeeded in moving thebackground data of the SMC memory bank for the DAM. Further more, it realizedefficient use of the shared storage data and the SMC parts’ function as a data cross path.2、The optimizations of cutting down power consumption and reducing the storageaccess delay. According to the storage fission control theory, it adjusted structure ofSMC parts, thus reducing the power consumption of SMC parts by80%. By usingstreamline operations and concurrent arbitration, it decreased the request delay of theDSP toward SMC parts by one clock cycle, hence enhancing the efficiency of thestorage access.3、The arbitration mechanism of combining fixed priority algorithm with looppriority algorithm. Based on the principle of fairness, when the request signals ofdifferent priority ask for the SMC memory at the same time, they gain access accordingto their order of requesting not because of the fixed priority, which leads to thephenomenon of “starvation” and “conspiracy”. In this way, it realized a more reasonablerequest order when the different request signals have structural relationship.4、The functional verification and logic synthesis of SMC parts. According to the X-DSPX systematic requirements, it completed the test vector development andvalidation for the SMC components, and by writing specific test program, it made thecode coverage rate of SMC parts reach more than99%. In addition, by using65nmstandard unit technical library to synthesize the SMC parts, the highest frequency of theSMC parts can be up to555MHz. Based on the systematic requirements of minimuminternal clock frequency of500MHz, the comprehensive result area of SMC parts is65783um2, and the power consumption is3.8692mW, meeting the systematicrequirements in design.