The Design And Verification Of Configurable Host Port Interface On DSP64X

DSP64X, a high-performance fixed-point digital processor independently developedby our university, has broad application prospects in many areas such as languages,graphics and images, signal processing and communications, etc.. Configurable hostparallel interface (Host-Port Interface abbr. HPI) is a parallel interface, an importantparallel interface unit for DSP to communicate with external system. By HPI, dataexchanges between external master system and DSP internal storage space can beachieved, and so do the bootstrap and debug of DSP chips. In the master-slavedual-computer DSP application system, direct dual-computer communication can berealized by configuring HPI interface.Main research contents and findings of this thesis:Based on the study of various configurable host parallel interface componentstechnology, this thesis has completed the overall structure design and protocol design ofconfigurable host parallel interface of this DSP according to the overall structure andperformance requirements of DSP64X.Based on DSP64X, this study has designed a powerful configurable host parallelinterface, and thus interface protocol between EDMA of DSP64X, peripheral buscontroller, interrupt controller and system controller has been achieved. HPI componentconsists of four function modules, namely, peripheral bus interface module, read cachecontrol module, write cache control module and EDMA interface module.By further studying the structure design of read and write cache, multi-cacheasynchronous docking technology with ping-pong structure has been achieved in thisthesis, and therefore, the parallel and high-speed data exchange between external host andDSP has been realized.Based on main verification methods of current microprocessor and requirements offunctional and structural characteristics of HPI, this study has completed the module-level,component-level and system-level simulation verification, developed complete testfunction code, and finished different levels of functional verification and timingverification, ensuring that configurable host parallel interface can meet the designrequirements and timing constraints.Based on Chip C7YC68013, this study has designed a simulation test platform,through which all functional verification and testing of DSP64X’s HPI component havebeen achieved.By actual chip test, the HPI component designed in this study functions well, with theexternal operating frequency up to200MHZ, parallel transfer of16-bit and32-bit datasupported, and the maximum data bandwidth up to800MB, which fully meets the requirements of the chip.