The Design And Application Of The On-chip Memory For YHFT-DSPX

Developing with the semiconductor manufacturing technology and computer architecture and others improvements, DSP has been widely used in communications, military, control, household appliances and other areas. Because DSP is generally for data-intensive applications, the speed and efficiency of memory access has a great impact on the performance of the processor, so the memory architecture is also one focus of the processor study.YHFT-DSPX is a high-performance 32-bit fix-point programmable digital signal processor that is designed by our school independently,which can run at 250MHz.The processor uses Very Long Instruction Word and Harvard architecture and has eight functions.All the eight functions run at the same time so that can improve the efficiecy of the code execution.Based on in-depth study for the functions and characteristics of the on-chip memory in this paper, we have divided it into two components that are named IDM and IPM, also analysed the DSP performance, and accomplished the structure and logical design of each component.This paper studied the process of fetching instruction, and successfully designed a memory access request for the initiation, the arbitration,the fetch packet submission ,memory orgnization and so on. For the cache hit failure case, by adding additional logic to judge the failure case,and to ensure the accuracy of the process of fetch packet. In addition, according to the features of the IDM, it allowed DMA and D components which include the DA and DB components simultaneous accessing IDM banks.That cause access conflict that is to access the overlapping destination address. We used a based on the priority of arbitration logical. The arbitration that is according to the PRI field of the DMA configuration registers and the assured priority between DA and DB determine access priority order, and also solved the overall impact of memory access performance bottleneck.We wrote a large number of codes that are being used for verifying on-chip memory, and also combined the simulation verification with FPGA verification to ensure that the function of the on-chip memory meet the design goals. In the Logic synthesis phase, we have given a full optimization strategy for on-chip memory, and made it achieved satisfied result both in timing and area .For the result of the chip test and application show that the designed on-chip memory which is based on the DSP reached to the established design performance, was able to meet high-performance DSP architetures and applications.