Continuous-time digital signal processors: Analysis and implementation | | Posted on:2009-08-28 | Degree:Ph.D | Type:Dissertation | | University:Columbia University | Candidate:Schell, Bob | Full Text:PDF | | GTID:1448390002491367 | Subject:Engineering | | Abstract/Summary: | | | This work describes digital signal processors (DSPs) that operate without a clock, or in continuous time (CT). The operation of these processors is different from that of an asynchronous system; in a CT system, the time duration between events is preserved. CT DSPs are compared to conventional DSPs (clocked at the Nyquist rate), and systems using CT DSPs are shown to have higher in-band signal-to-distortion ratios. Spectral properties of systems using CT DSPs are also investigated, demonstrating that---due to a lack of aliasing (as there is no sampling)---the spectrum at the output of a CT DSP system will contain only frequency components related to the input frequencies.; Attention then turns to the hardware implementation of a system that uses a CT DSP. Such a system necessarily uses a CT ADC (an ADC that does not use a sampling clock in its conversion) to convert the analog input into a digital word to be processed. The lack of a clock complicates the task of creating delay; this issue is addressed with custom CT delay cells. This work focuses on transversal direct-form finite impulse response (FIR) and infinite impulse response (IIR) filter design as a realization of the CT DSP, each design requiring CT delay elements. The digital core of the CT DSP is designed without the aid of a clock, using asynchronous techniques. Extensive handshaking is used to avoid glitches.; A test chip has been fabricated to verify the theoretical claims and validate the design of the CT DSP system. The test chip, fabricated in a UMC 90 nm CMOS process, is a CT DSP system that operates at up to 20 kHz using a CT ADC resolution of 8 bits and by design does not have glitches in the 8-bit output word. The CT DSP system dissipates nearly 3.1 mW for a full-scale 20-kHz input sinusoid when configured as a 16-tap FIR filter. The power consumption is shown to track input activity automatically, without the use of a power-management scheme. | | Keywords/Search Tags: | CT DSP, Digital, Processors, CT dsps, Clock, Input | | Related items |
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