FPGA Implementation Of Intra Frame Decoder For H.264

H.264 is the latest multimedia compression standard promulgated in May 2003. It uses a lot of the latest video encoding technology. Compared with the previous standard, the compression efficiency and flexibility has been greatly improved. Now it's widely used in multimedia transmission, storage, etc.This dissertation mainly discusses the hardware implementation of intra frame decoder for H.264, including inverse quantization, inverse transform and intra prediction. The contributions of the paper are summarized as follows:(1) With Top-Down method,the H.264 intra frame decoder was divided into four main parts, including inverse quantization, inverse transform, intra prediction and macroblock reconstruction prior to deblocking filter. Then the first three modules were detailed, including function, hardware architecture and operation timing.(2) To save hadware resources, by analyzing and extracting the reusable parts of inverse quantization, inverse quantization and intra prediction, a reusable computing unit was designed, which could be used by each module. Meanwhile, to meet real-time requirements, A four-pixels-parallel decoding method was adopted to accelerate decoding speed.(3) For intra prediction module, to save storage resources and reduce power consumption of memory access, a three-tier reference pixel storage structure was proposed, by which the memory units of reference pixel was composed of line buffer, macroblock-level registers and 4x4 block-level registers.(4) The dissertation fullfilled the RTL coding, functional simulation and a FPGA prototype implementation of the H.264 intra frame decoder. Demo based verification was achieved through decoding real-applied video stream, result of verification shows that the design can support real-time decoding with H.264 main profile video sequences.