Optimization And Hardware Realization For H.264 Intra Prediction Decoder

H.264 is the new video compression technical standard composed by JVT (Joint Video Team) which ITU (International Telecommunication Union) and ISO (International Organization for Standardization) two big organization make up together. Providing the high-grade image transmission in a lower band width is the H.264/AVC application luminous spot. Under the similar visual quality premise, H.264/AVC saved 50% bitrate compared to H.263 and MPEG-4. But the high complexity comes with the high performance, it is estimated its encoding complex probably is 3 times as the H.263, thus only software implementation is difficult to apply in the real-time video processing domain. The design of decoder must be implemented with the hardware and software working together.The main thesis of the paper is the optimization and hardware implementation for H.264 intra prediction decoder, which is mainly used in hand-held consumer devices. Since the hand-held consumer devices have almost harsh requirements for power consumption, the focal and difficult point of the paper is the implementation of high efficient hardware with low frequency. The paper focuses on the implementation of efficient intra predication decoder with low power. It exploits power saving potentials spanning architectural and circuit levels. The research results are as follows:1. At the architectural level, parallel element units and self-adoptive pipeline are adopted to reduce the operating frequency. The self-adoptive pipeline can adjust the stage of pipeline according to intra prediction mode. It not only helps to save power since it reduces the design frequency and eliminate the redundant cycles, but also reduce latency.2. At the circuit level, reconfigurations are adopted to calculate the predictive value. The two-level seed scheme is proposed to calculate the predictive value of plane mode. The multiplications, which account for large chip area and switching power, are eliminated.3. Finally, The design of intra prediction Decoder is implemented with hardware. The design of intra prediction decoder is realized with Verilog HDL. The simulation and synthesis result indicate that the design can achieve 30 f/s for resolution QCIF format video at 58.82 MHz with an area of 4921 logic elements. The power consumption is 251.28mw, which meets the design requirement.