Parallel Hardware Design Of Intra Frame Coding Algorithm Of Video Compression Standard H.264

Real-time video processing is widely used in areas such as multimedia, video communication and so on. With the development of video compression standard, the algorithm and data become much more complicated, it is difficult to meet the real-time system requirement for video compression running in software mode. The rapid development of FPGA technology provides a programmable platform for hardware implementation of the complex algorithms, and the research of hardware implementation of video coding algorithm has become a hotspot. This paper implements intra coding algorithm of video compression standard H.264 by using a high-level language Handel-C, and completed the simulation and FPGA verification of algorithm.This paper compares the different ways of hardware implementation of the algorithm between hardware description language and high-level language, and talks about the advantage of high-level hardware implementation language, the characteristic and development processes of Handel-C language has also been researched.This paper chooses the Handel-C language which supports parallel logic for hardware design. This paper divides intra coding algorithm of H.264 into transform, quantization and entropy coding and some other function modules by analyzing the H.264 encoder structure. The basic principle of each module is studied in detail, and the major contributions are outlined as follows:1. The method of hardware implementation of intra coding algorithm of video compression standard H.264 based on Handel-C is proposed. All the modules has been designed and implemented by using Handel-C language.2. The quantization module and transform module are integrated together. And it makes calculation easier in integer domain for this integral. A suitable looking-table structure is designed for the CAVLC algorithm, which improves the system coding speed.3. By using the parallel logic function of Handel-C, each module has been optimized and improved. And it implements the parallel algorithm effectively in the use of limited hardware resources.4. This paper built a software/hardware co-design platform, and put forward the verification solution of H.264 intra coding algorithm based on HPS. Then, all the modules are simulated and verified on Altera’s DE1-So C board. The verification results show that the hardware modules of H.264 intra coding algorithm designed by using Handel-C language can work well with software.This Paper’s work might be helpful and instructive to the later research on algorithm-hardening in Handel-C language and development of video compression standard.