On The FPGA Design And Implementation Of The Turbo Encoder And Decoder Based On Frame Splitting And Trellis Zero Terminating

In the modern digital communication system, error control coding is an important technique to guarantee the reliable message transmission over noisy channel. Turbo codes have become a hotspot due to its excellent error control capability since its first presentation. Nowadays, Turbo codes have been widely used in deep-space communication system, satellite communication system and mobile communication system. And the basis for the application of Turbo codes is the codec design and implementation. With the evolution in communication techniques, there is an increasing requirement in the high speed Turbo codec design and its implementation. Therefore, it is of practical importance to investigate the Turbo codec with high data rate processing capability.However, the recursive computation and the iterative calculations are the primary difficulty and barrier for improving the decoding throughput. Besides increasing the processing frequency clock of the chips utilized, parallel decoding structure and the related implementation scheme need investigations as well. In parallel decoding scheme, a long code block will be divided into multiple subblocks, which will be proceeded by multiple SISO cores simultaneously, thus greatly reducing the decoding delay and improving the decoding throughput. In order to combat the performance degradation, overlapping between neighboring sub-blocks and the passing of the state variables between iterations are always needed. But the redundant bits owing to the overlapping between neighboring sub-blocks will decrease the computation efficiency to some extent. And the passing of the state variables between iterations will consume extra memories and impose additional control overhead. The frame splitting and the trellis zero terminating Turbo encoding scheme will impose the inherent sub-block structural property with a small decrease in the coding efficiency, such that neither the overlapping between neighboring subblocks nor the passing of the state variable values are not needed any more in the codec design and implementation to avoid the performance degradation. And how to design and implement the codec for the frame splitting and the trellis zero terminating Turbo codes is exactly the topic of this thesis.The thesis is organized as follows. Firstly, the thesis compares performance of the frame splitting and trellis zero terminating Turbo codes and the conventional Turbo codes for the 3GPP-LTE standard component codes and interleaver through simulations. Meanwhile, the sliding windows decoding mechanism, together with the IHDA stopping criterion, are investigated through simulations in the thesis to validate their applicability in the frame splitting and trellis zero terminating Turbo codes. Based on the subblock sizes validated through simulations, the thesis discusses in detail the design and the functional validation of the frame splitting and trellis zero terminating Turbo codec. Finally, the resource utilization of the realized Turbo codec, the achieved processing throughput efficiency, and the achieved reliability performance of the implemented fixed point Turbo codes are presented to validate the correctness of the design in the thesis.And the related analysis, the FPGA design and implementation unveils that, the frame splitting and trellis zero terminating Turbo code is capable of achieving the similar reliability as the 3GPP-LTE Turbo codes. Moreover, the analysis in this thesis convinces us that, the frame splitting and the trellis zero terminating are the effective mechanisms to create the inherent segmented trellis structure in the Turbo codes to make the corresponding Turbo decoder codec design have the following two advantages: Firstly, there is no need to consider the overlapping between neighboring subblocks to guarantee the decoding performance. As a result, each SISO module only needs to proceed a smaller subblock, which is highly desirable for the decoding throughput improvement, especially for the short frame size case. Secondly, the trellis zero termination encoding means that the initial and end state for each subblock is determined as the all-zeros state instead of being unknown, which will make the decoding in multiple SISO modules independent of each other. Since both the forward and backward recursive state metrics could be initiated from the known all-zeros state, the complicated control design for exchanging both state metrics between iterations become unnecessary. As a conclusion, the work in this thesis validates the fact that, the Turbo codes with frame splitting and trellis zero termination offers the feasible and effective alternative for the high speed Turbo codec techniques in practical applications.