Research And Design Of Intra Prediction And Deblock Filter In AVS Video Decoder Based On FPGA

The application of multimedia video compression technique grows very rapidly with the development of information technology and digital signal processing transmission. Image compression technology is got more and more attention.In order to avoid high patent costs of H.264 international standards, satisfy the demand of information industrial development, in 2002, China began started to organize related enterprises and research institutes develop our own audio and video compression standards AVS. AVS has already become the China national video coding standard and AVS has high compressing rate, high video quality and low royalty, etc... Based on AVS intra prediction and loop filter module design and implementation of FPGA as the topic, in promoting China’s AVS digital video codec standard applications and industrial development has important theoretical significance and practical application value.At first, basic knowledge of AVS and FPGA is introduced briefly in the paper.Then the architectures of two important modules which is Intra prediction and Loop filter in AVS coder researched and discussed deeply in the paper.According to AVS standard, we improve the arithmetic of intra prediction mode selection. It proposes a general processing element which improves the reusability of hardware resources and reduces the computational complexity of intra prediction, In order to improve the processing speed, plane mode precomputation and effective control logic are adopted. A five-stage pipeline is adopted to improve throughput. The hybrid edge filter order is developed to deal with pipeline hazards. Transposition module is suitable to transposing pixels. State machine is used to control the design, and according to horizontal filter, vertieal filter, different bound-strength, adaptive process is carried out. In this paper, we use the top-down design approach to divide the sub-module. These modules mentioned above were actualized on RTL level by Verilog HDL,simulated in Modelsim,synthesized in QuartusⅡ8.0.The verification and simulation results indicate that the design of Intra-prediction and Deblocking-filter has achieved requirement. The paper carries out a good research for AVS video decoding system based on FPGA and it provides a degree of application value.