| As today's design getting bigger in size and more complex than ever, die size becomes bigger and bigger, working frequency of the chip getting higher and higher, yield becomes a big problem. The cost of testing became an important part of the chip design.This paper describes the DFT design for a UWB MAC chip. The design includs scan chain, MBIST and JTAG. It proposes a method for adaptive scan by which will lower the testing time to 8% of the testing time comparng with basic scan, therefore reducing the cost of testing. It also proposes an at speed test circuit which uses on-chip clock and test clock for logic and memory. And finally it provides a flow on how to use a diagnosis flow for the circuit fault, locate the root cause of pattern failure, optimize the design and improve yield. |
