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Research Of The Fault-detect And Fault-tolerant Methods On Router In Network-on-Chip

Posted on:2016-05-11Degree:MasterType:Thesis
Country:ChinaCandidate:Y J ChenFull Text:PDF
GTID:2308330473957078Subject:Computer technology
Abstract/Summary:PDF Full Text Request
Compared with traditional bus-based System on Chip, Network on Chip has the advantage of strong scalability, low delay and high bandwidth. However, with the scale of integrated circuit increasing and the size of transistors shrinking, manufacturing defects, soft errors and aging would lead to the increase of the chip’s fault rate. According to the mentioned problems above, it is necessary to design a fault-tolerant architecture for Network on Chip. Thus, based on the fault detection and fault tolerance, contributions of this paper aiming at solving the reliability problems brought by routers in Network on Chip are as follows:(1) This thesis proposes a new fault model called channel fault model for the soft or hard faults occurring in the input buffer and the crossbar of a router in Network on Chip. Meanwhile, this paper designs an isolated channel detection method to isolate the channel detection from the data transmission. Channel fault model defines all the components that the data passes from entering a router to leaving a router as a channel. If the data is error after going by this channel, the method will disable this channel. At this time, isolated channel fault detect method diagnoses the fault channel without disturbing other fault-free components in the router, further determines the fault types of the fault channel (soft errors or hard faults). Experimental results show that the fault-tolerant router architecture with the proposed fault model has a low-overhead and the isolated channel fault detect method affects the performance of the whole system less than other methods.(2) To tolerate the faults that occur in the channels of a router in Network on Chip, we propose a effective low-overhead solution. Firsty, the solution uses some clever combination of existing technology to reduce the router basic transmission delay and overhead. Secondly, if there is a soft error in the channel, we will use the buffer which is equipped with recycle pointers to retransmit fault data; if hard faults happen in the channels, the method will use the redundant channel to transfer the data to replace the fault channels. A buffer with a recycle pointer could greatly reduce the area overhead and power consumption brought by retransmission buffer. However, the fault tolerant redundant channel achieves the interconnection of the whole network at the cost of the minimum overhead when there are faults in the network. The experimental results show that the network performance of the proposed scheme in any case is superior to the reference objects, and the proposed scheme has smaller fault-tolerant overhead compared with the reference objucts.
Keywords/Search Tags:network on chip, fault-tolerance, reliable communication, fault detection
PDF Full Text Request
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