Design Of Decoder For LDPC Codes Based On FPGA

LDPC code, i.e., low-density parity check code, was proposed by MIT PhD Gallager in 1962 in his doctoral thesis. It can approach the Shannon limit. LDPC codes have become IEEE 802.16e, UWB and WiMax standard codec schemes, and become the next generation mobile communication standard.This design uses FPGA hardware as a full parallel decoding circuit design platform. The decoding algorithm uses soft decision algorithms on probabilistic domain. Tanh function and anti-tanh function of the decoding algorithm are implemented through the look-up table of FPGA.The design of the main work was done as following:1, improved data access ability to read, saving the data read time. C language pointer operation is realized in FPGA, the LDPC code parity check matrix that is sparse matrix can stores only 1 position, greatly saves the storage resources, improve the data access ability, save the data access time.2, the introduction of ping-pong operation method facilitate the seamless buffer and the processing of data. Decoding module implements the uninterrupted work by eliminating data read pauses.3, C++ liked Token-Pasting Operator is successfully applied in FPGA applications by using the strengthend macro definition of SystemVerilog which facilitates the instantiation of variable nodes and check nodes, and greatly reduce the quantity of writing code.In the clock frequency of 500MHz, the decoding speed is 0.24Gbps with the iteration number of 20 times.