Research On Decoder Design For Non-binary LDPC Codes

With the development of communication theory and VLSI, LDPC codes have been widely used in communication standards because of their excellent error correction capability. As an extension of binary LDPC, Non-binary low-density parity-check (NBLDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. This paper presents the design of memory efficient QC-NBLDPC decoders based on extended min-sum (EMS) algorithm and the efficient partial parallel symbol reliability based (SRB) algorithm and its VLSI implementation.This paper presents a layered EMS algorithm for generic QC-NBLDPC codes based on traditional EMS decoding algorithm. The simulation results show the layered approach can effectively reduce average number of decoding by30%, which is very helpful to increase the throughput.To improve the memory efficiency, a novel message access scheme and message quantization method is explored. While maintaining the necessary error correction performance, the memory consumption is significantly reduced. We applied the novel scheme to the QC-NBLDPC codes and found the proposed design is more efficient.Based on the serial symbol reliability decoding algorithm, this dissertation presents a highly efficient and low complexity partial parallel decoding algorithm, which can reduce the hardware consumption greatly. The corresponding decoder architecture is presented.