Non - Binary Ldpc Code Decoder Design And Implementation

Low-density parity check codes were first introduced by Gallager, along with several message-passing decoding algorithms. It has been shown that binary LDPC codes, when decoded using belief-propagation decoding (BP) algorithm, can approach the capacity of the AWGN channel. However, binary LDPC codes start to show weakness when the code length is short or when a high-order modulation is applied in communication system. It has been approved that the performance of binary LDPC codes can be significantly enhanced by a direct extension to a higher order Galois field. Therefore, designing high-performance NB-LDPC decoder is now one of the hotspots.Based on analysis of Sum-product algorithm (SPA), MAX-LOG-SPA and other decoding algorithms, a new algorithm oriented hardware implementation, named HOM-LOG-SPA, was proposed in this thesis. HOM-LOG-SPA is one of belief propagation algorithms on log-domain, based on MAX-LOG-SPA and only summation and comparison are contained. Due to the special construction of symbol vectors, which satisfy parity check function, origin summation and comparison are calculated by divided into layer (LSC). Comparing with MAX-LOG-SPA, the computing complexity of vertical step is reduced by p-2, where p is row weight of parity check matrix. As a result, the total computing complexity of HOM-LOG-SPA is reduced effectively. These tow algorithms have same decoding performance, and very slight performance lose comparing with SPA.A NB-LDPC decoder architecture based on LSC is proposed after algorithm simulation. Also, a special RAM architecture is used in this decoder to solve problems resulted by parallel computing, such as data dependency, memory access conflicts, etc.Based on the study of above key techniques, a normal purpose regular NB-LDPC decoder over finite Galois field is designed and implemented. The above key techniques are tested and verified over a NB-LDPC transceiver system base on FPGA.