The Simulation And Design Of The Quasi-cyclic Ldpc Decoder In T-mmb Standard

The current mobile TV system for mobile phones offer digital audio and video information, allowing users to access the latest information anytime, anywhere and the highest quality information, so the current mobile TV a very broad application prospects.This paper studies found T-MMB mobile TV standard channel decoder hardware implementation. First systematic introduction to LDPC codes decoding principle, analyzed and normalized minimum iteration update formula and QC-LDPC coding method.In the analysis of the minimum and normalized algorithm based on the T-MMB standard requirements of the QC-LDPC parity check matrix, it was proposed quasi-cyclic LDPC decoder FPGA Implementation, and gives the main hardware design, gate-level simulation and hardware decoding results.Alignment cyclic LDPC decoding method of the hardware resources and throughput comparison of balance, given the simplified algorithm for FPGA implementation, and for the FPGA XILINX's Virtex4 series is optimized hardware platform, the decoder with VerilogHDL Description Language programming.Functional modules in the implementation process, the proposed based on "indicators" of the search method of the smallest second smallest value. Compared with the classical method step by step "assembly line" structure, the new method is introduced to a software programming in the "pointers" concept, thinking the software into a hardware implementation, the level of operation of the unit were optimized. Finally, Matlab on T-MMB system transmitter was simulated on the energy source of information for the proliferation of LDPC coding, 8PSK modulation, plus noise, soft decision; and analyze the performance of decoder and error rate.In this paper, the T-MMB system simulation and the QC-LDPC decoder implementation of the mobile TV decoder to do some exploration and research, to other standard mobile TV also has a certain reference value for reference.