Research Of Timing-skew Background Calibration Technique For TIADCs Based On Zero-Crossing Detection

As a key circuit of conversion from analog to digital signal, analog to digital converter (Analog-to-Digital converter ADC) plays a very important role in modern communication, image acquisition, medical electronics and other fields. However, single channel ADC in academia and industry has tended to be mature, the performance of the system has been gradually approaching its limit. Time-interleaved ADC (Time-Interleaved ADC, TIADC) is an effective method to maintain the conversion precision of single ADC and improve the system sampling ratein multiply. But due to the error of integrated circuit technology, there exits mismatch errors among each sub-channel of time-interleaved ADC, and result in spurious spectrum in output spectrum of time-interleaved ADC, which seriously affect the dynamic performance of the system.This dissertation analyzes the error source and formation principle of time-interleaved ADC’s three main mismatch errors (offset mismatch, gain mismatch and sampling time mismatch). On this basis, this dissertation studies the zero crossing detection algorithm to calibrate sampling time mismatch error, which is the most difficult to calibrate among the three kinds of mismatch. Without strict requirement on the input frequency and number of channels, the calibration algorithm can effectively eliminate the effects of sampling time mismatch.Firstly, a 2.5GHz 8-bit 5-channel TIADC calibration model was built with MATLAB/Simulink. Simulation results with normalized frequency fin/fs=0.461 show that, ENOB improves from 4.58bits to 7.82bits with the proposed calibration method, which verifies the correctness and effectiveness of the calibration algorithm; secondly, RTL code for the error estimation of the calibration algorithm was designed, and function simulation with Modelsim was accomplished. Finally, the analog circuit for error correction and digital circuit for error estimation are combined in Cadence AMS to simulate using TSMC 0.35um CMOS process. The simulation results show that ENOB has an improvement of 3.77bits, which further prove the validity and practicability of the proposed calibration algorithm for the sampling time mismatch.