Implementation Of CCSDS Satellite Image Compression System With FPGAs

The Consultative Committee for Space Data System (CCSDS) data compression working group released the standard for image compression in 2005. The standard, which adopts BPE(bit plane encoder) basing on DWT, not only supports both lossy and lossless encoding and precise bitrate control, but also has good capacity for error resistance and very high performance of image compression, so the standard can meet the various needs of practical application. Meanwhile, a low complexity, easy to implement on hardware in low power and a high adaptability of satellite image makes the standard have great potential in aerospace applications.This thesis mainly focus on hardware implementation of the CCSDS image compression algorithm by using FPGA in the situation of limited hardware resources. In this paper, a solution of the CCSDS image compression encoder, with high speed and efficiency, has been introduced and implemented on a exiting hardware platform of FPGA. First, the fundamental principle of the CCSDS image compression algorithm is introduced in detail. Then, the parallel hardware implementations of the DWT,BPE and stream organization are given. Also, the paper proposes a solution of the simulation platform which can be used for batch simulation test. Finally, the results of tests on the platform of Xilinx VIRTEX-II FPGA showed that the various technical indicators of the CCSDS image compression system are proved to meet the requirements of image compression in aerospace applications.