The Design Of Key Circuit Units For Two-Step Pipelined A/D Converter

Analog-to-digital converter provides the link between the analog world and digital systems, and it acts as a bridge in signal processing and conversion. In this thesis, we study a 10-bit A/D converter which has the features of 1 V input range and 40 MS/s under 5 V power supply.Some architectures of A/D converters which can achieve the performance are compared. Two-step architecture offers both low latency , small chip area and reasonable amounts of hardware as compared to pipelined converters, together with low power consumption. Due to the above advantages, this approach is adopted. Furthermore, avoiding the errors along with the high gain amplifiers is another obvious merit of two-step architecture. By inserting inter-stage sample-and-hold circuits, conversion rates can be enhanced, the circuit can work pipelined and the architecture is improved consequently. With the use of fully differential architecture, the charge injection effect is decreased, common-mode noise is suppressed due to supply transients and substrate coupling, the input dynamic range is increased and even-order harmonic distortion can be eliminated.The main error sources which affect performance of the ADC is analyzed and a few solution is also presented. In this thesis, we mainly accomplish the design of the basic circuit units , such as the design of input buffer, sample-and-hold circuit, differential resistive ladder, coarse and fine comparator, bandgap voltage reference and current reference .In order to achieve the objective of optimize accuracy and power dissipation, the configuration of front-end and inter-stage sample-and-hold circuit is adjusted due to the differences between input signal of front-end and inter-stage sample-and-hold circuit. Because of adopting large number of comparators, the speed and power dissipation will be the important affective factors of ADC performance. The tradeoff between speed and power dissipation is roughly analyzed with the help of some references.Based on Chartered 0.35um double-well 2P3M BiCMOS process, the simulation and optimization of circuit is accomplished and the simulation results are obtained with Cadence Spectre. The conversion time of three S/H circuits are 7.57ns,4.72ns and 8.1ns at 40MHz ,respectively. The response time of coarse and fine comparator are 4.39ns and 4.91ns at an overdrive voltage of 0.5mV, respectively. The temperature coefficient of output voltage reference is 15.2ppm/℃in the range of -45℃~85℃, the power supply rejection ratio is 60dB. The output current of current reference at room temperature is 74.16uA . The relative error is 0.78% in -45℃~85℃, which is greater than required 0.5%. If the whole ADC works in the normal temperature range, error range can be less than 0.5%. It is sufficient to achieve the accuracy of ADC. The simulation results show that the requirement of the performance of circuit units can be well achieved.