Font Size: a A A

Design Of 65nm SRAM

Posted on:2011-12-01Degree:MasterType:Thesis
Country:ChinaCandidate:Q ZhangFull Text:PDF
GTID:2178360302489908Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
With the development of semiconductor technology, the feature size of transistor is shrinking down to tens of nanometer. As results, its speed continuosly increases. Howerer, process fluctuations also increases with the shrikage and brings more challenges to SRAM design.Aimed at increasing speed, reducing power and area, suppressing process fluctuations, this thesis designed a 1024x32 SRAM based on the research of 65nm SRAM architecture. The layout is 0.0376 mm2, the average current is 4.3mA and the CLK to Q is 0.548ns in post simulation. The main content is as follows:1. Through research on SRAM MUX, the performances of one-tier and two-tier architecture and the corresponding single and dual structures were analyzed theoretically, from which it was derived that the larger the characteristic number of sense amplifier, the better the two-tier architecture in comparison with one-tier one. The optimum two-tier architecture is achieved when the characteristic numbers of the two-stage decoder are close. The optimum two-tier architecture could reduce up to 33.6% of read access time compared with the conventional one-tier one.2. SRAM clock generator was analyzed and researched in details. The performances of two mainstream discharge circuits was analyzed and compared based on probability. And the the results were verified by one hundred thousand Monte Carlo simulations. Based on it, the better discharge circuit was chosen to build the clock generator. The clock generator is capable of well coordinating the different part of SRAM. Besides, it can dynamically adjust the access speed for manufactured chip.3. Through analyzing and researching the SRAM decoder circuit, the important factors in SRAM design were derived and the design methodology for low power and fast access decoder was introduced. Meanwhile, the application of logical effort theory to decoder design was discussed and expounded. Finally, the circuit model of asymmetric logical gates was built and its application to decoder design was introduced based on analysis of its advantages.
Keywords/Search Tags:SRAM, MUX, clock generator, decoder
PDF Full Text Request
Related items