Design And Analysis Of CMOS PLL Clock Generator

With the development of semiconductor process technology, nowadays a system on a PCB (Printed Circuit Board) which is composed of several ICs can be integrated into a chip. The derivation of SOC (System on a Chip) is based on this ideology. SOC can improve the system performance greatly and solve various problems which may occur in a PCB system such as noise, speed limit, etc.While SOC brings more facilities to users, more chanllenges are presented to the designers. As is known to all, the former PCB system uses an out-chip oscillator, which is called out-chip clock generator, to provide system with clocks. However in SOC or high performance CPU an in-chip high quality clock is required to guarantee the timing of all chips. But to design and integrate a clock generator into a chip is a far cry from the out-chip one. The implementation of in-chip clock generator is often based on modern CMOS IC process technology which is usually adopted by very large scale digital system. While designing a deep sub-micrometer CMOS circuit, delay, power consumption and die size are of the main factors that must be considered. Above all, using the proper circuit structure to meet the SOC requirement is the essential issue.PLL referred in this thesis is aimed to generate system clock. The concept of phase locking was invented in the 1930s and swiftly found wide usage in electronics and communication. Today a new application of PLL is a great challenge for IC designers to integrate it into an SOC .This PLL clock generator is designed for an SOC chip -"LINE"(LINE is an SOC based on an embed 32-bit microprocessor C*Core ,which is used in telephone with short message service function, and it can provide the system with multi-frequency clock signals ranging from 93.75KHz to 180MHz. Within this scope, users can get almost any frequency clock by configuring the register, as the tune-process is nearly continual (in fact there are many discrete frequency points).The main circuit of the clock generator is a CPPLL (Charge Pump PLL) designed in a method. It consists of several sub circuits: PFD (Phase Frequency Detector), CP (Charge Pump), LP (Loop Filter), VCO (Voltage Control Oscillator) and some auxiliary circuits. The thesis will emphasize the design of loop circuits which comprise PFD, CP, LP and VCO in chap3-5, and the analysis of loop performance is also very important. To comply with thelow-power-consumption application, low-voltage design is taken into account by using some special circuit structures. . Besides there are many nonideal effects in PLL which degrade the loop performance badly, some efficient solutions have been put forward to suppress the undesired ones.The PLL clock generator, which has been integrated in "LINE", will be taped out through TSMC 0.25um MPW (Multi-Project Wafer) project.