Hardware Designfor 3D Real-time Video Capture System Based On Camera Array

With the further development of 3D techniques and growing demand on 3D product, 3D video capture techniques of hardware platform tends to be real time become more and more important. In light of complex synchronization, high power dissipation, high cost, low stability and low portability of current 3D video capture techniques, this paper proposes a camera array and high performance digital media processor (DMP) based 3D real time video capture system. Circuit board implementation, whole hardware platform construction and most software test are also accomplished.This paper firstly analizes the structure characteristics of current 3D real time video capture systems and points out their deficiencies. A design proposal on CMOS sensor based camera array and high performance digital meida processor TMS320DM648 based 3D real time video capture system is put forward in this paper. This design proposal ensures low power consumption, high stability and low cost on the premise of achieving high definition video capturing and processing.Second part of this paper elaborates on overall framework of hardware design on 3D real time video capture system. Whole system is divided as three subsystems, say video capture subsystem, data distributed subsystem and video processing subsystem. Further we deep in three subsystems' board architecture and implemented function. Finally an LVDS serialized connection pattern is selected as a suited selection of interconnection of subsystems.Third part of this paper introduces the concrete design of function modules in the system, including logic timing module, video capture module, video frame synchronous module, board interconnection module, power supply module, DDR2 module, FLASH module, Gigabit Ethernet module and video port module.The last part is on the software and hardware implemented and debugging of 3D real time video capture system. Firstly we emphasize on key technique of hardware board PCB design, i.e. LVDS signals design and DDR2 signals design. Finally software debugging procedure is illuminated. And conclusion follows.