Design technique of fractional-N delta-sigma frequency synthesizer for wireless communication in 0.5 micron silicon germanium

This dissertation presents the design of RF synthesizer by the fractional- N Delta-Sigma modulation technique in 0.5μm Silicon Germanium BiCMOS process. Key merits of the fractional-N Delta-Sigma frequency synthesizer have been discussed in detail. A dual-loop scheme of phase-locked loop frequency synthesis topology is adopted for wide-range and very fast frequency acquisition. Delta-Sigma modulator provides fractional divide number control with shaped passband noise, which alleviates the disturbance of random white noise from fractional number control and provides fine frequency step for applications.; Two prototype fractional-N frequency synthesizers demonstrate good performance, low power consumption, and high level integration achieved with this proposed design approaches and SiGe IC process. Handset synthesizer prototype achieves a low phase noise of −108dBc/Hz at 100kHz offset and a low side band spur of −85dBc at 1.6MHz offset with 18mA current consumption and 1.5GHz carrier frequency. The measured results fully satisfy the system requirements of personal digital communication (PDC) and wireless integrated network sensors (WINS) applications. Basestation synthesizer prototype has a very fast locking time of 67μs for 100MHz frequency switching and achieves a low in-band phase noise of −94dBc/Hz at 10kHz offset with 13mA current consumption, which can be applied to many standards of mobile RF communications.