The Research & Design On 64-bit 1.47GHz High-Performance Integer Adder

This thesis emphasizes on design methodology of the 64-bit high performance integer adder,it is one of the important algorithm components in the X stream microprocessor. In order to achieve faster speed and smaller area,full custom design methodology and dynamic domino logic has been adopted together. This thesis mainly contributes to the following aspects.1. Design and Implementation of a High-Performence 64-bit integer adder by using full-custom design methodology and dynamic circuits. The ultimate simulating result of the layout shows that the delay of the critical path is about 680ps, which is measured under the condition of SS and 130nm technology. After compare with other 64-bit adders and analyze,we have known that the design have taken advantages over others in speed,area and power consumption.2. Because of the dynamic circuit is high-speed but sensitive to the noise, the paper analyzes deeply the bad influence on the dynamic nodes which is produced by the noise.according to the characteristics of the dynamic domino logic,the paper has put forward a method for optimizing it—Skewed CMOS logic optimization.this method makes the dynamic domino logic reach the balance between the speed and noise tolerance.3. In order to find the circuit structure which can help to realize high-speed adder,the paper has analyzed and researched deeply on the parallel-prefix algorithm which it is popularly applyed today and several kinds of advanced carry-tree structures implemented by it.Through the research,we have found that the traditional Han-Carlson tree has better performance on the logic-levels,routing-channels and maximum fanouts.on the basis,the paper brings forward scheme about improving the traditional Han-Carlson tree,and it proves that the improved Han-Carlson tree has very excellent capability.otherwise,the paper also discusses about its circuit form;in order to assure the total performance of the adder,the paper has also do a large number of research and optimization work on the circuit.4. Adopting the design flow of hierarchical full-custom layout to design adder's layout,in order to achieve higher performance and smaller area,the floorplan is decided so elaborately and adjusted,optimized so iteratively that the ultimate design meets requirements.otherwise,the paper also analyzes deeply on the technologies about how to optimize the delay brought about by the long wire under DSM process.