A Custom Design Of Adder For DSP Hard IP Core

The adder is a very important arithmetic unit for high performancemicro-controller and digital signal processor. Nowadays, high-performance adder is notonly used in math arithmetic, but also playing a real important role in encryption, imageand voice signal processing. The performance of adder will directly affect the speed ofwhole system, and have a great impact on the frequency of the chip. Therefore,designing and optimizing the structure of the adder will enhance the overall speed, havea lower area and power consumption.This paper completed a design of three-input48-bits adder/subtractor-specialmodule in a FPGA chip of a DSP hard core, which based on a deep research of thetheory of adder. In the structure of the design, that through the combinational logic witha3:2compression and carry-in signal and addition and subtraction signal simplify thethree sets of48-bit input into two groups of48-bit. Through a comparative analysis the48-bit adder use the structure, which based on the carry-select and mixed tree. thisstructure calculations the carry output set of signal, which order is four, and use thesignal to select the correct result of output. The underlying logic use the CPL circuit toachieve in this design. After completing the design of the module, a verification of thedesign is necessary. And the results of simulation indicated that the des ign had met theinitial objectives.