Study Of Deep Submicron Strained Silicon Devices By Simulation

With the rapid development of integrated circuit (IC) technology, the feature size of transistors has advanced to the deep submicron, or even ultra-deep submicron (nanometer) level. Improving the performance of current mainframe CMOS devices by continuing using the scaling rule has encountered more and more physical and process limitations. It is thus necessary to study new materials, new properties and novel structures compatible with current Si process technology so that the high developing speed of IC technology predicted by Moore's Law can be maintained. This has been commonly acknolowdged by both academic researchers and industry experts.Recently, strained Si technology and novel FinFET structure have attracted wide attention due to their excellent performance in boosting CMOS properties. Take the typical CMOS strained Si device as an example, the compressive channel stress in PMOS device can usually be produced by epitaxial SiGe source/drain or depositing SiN compressive liner. The hole mobility can be increased by controlling the amount of compressive strain. As a result, the device performance can thus be improved. On the other hand, the tensile channel stress in NMOS device can usually be introduced by the stress memory technology (SMT) and depositing SiN tensile liner. The electron mobility, as well as the device performance, can be enhanced by controlling the amount of tensile strain. Therefore, optimizing the process and structure parameters of deep submicron or nanoscale semiconductor devices, studying the effect of stress on device characteristics, are of great importance for science and practical applications.In most cases, however, the accurate measurement of local microscopic stress and strain in (ultra) deep sub-micron semiconductor structures must resort to complicated microstructure analysis tools. Since there is little work reporting the domestic research progress in the stress distribution and the stress-device performance relationship by experiment, this thesis attempted to investigate these new semiconductor structures by two-dimensional simulation using TCAD tools. The emphasis was put on the possibility of introducing the strain engineering into CMOS devices and their effects on device performance. Besides, three-dimensional simulation study was also performed on Omega FinFET.In the practical work, the typical stained Si CMOS device was firstly investigated by Sentaurus. The simulaton results indicated that some key electrical characteristics, such as the on-off current ratio (Ion/Ioff) of the device was in good agreement with experimentally measured data in devices manufactured using the similar process technology, verifying the correctness of the adopted model and technology roadmap. Secondly, various stress introduction combinations were proposed. The dependence of stress distribution on device parameters was obtained by simulation. The results showed that key electrical performance, such as the threshold voltage, Ion-Ioff and sub-threshold characteristics, could be significantly improved by the stress engineering. The CMOS device performance was thus significantly enhanced. Moreover, the dependence of channel stress and device performance on the Ge molar fraction in PMOS, as well as the similar dependence on the intrinsic stress and thickness of SiN liner in NMOS was studied systematically. The electrical characteristics of Omega FinFET was finally investigated by three-dimensional Sentaurus simulation. The obtained reasonable results verified the correctness of the simulation method. In-depth studying of other electrical characteristics was further performed. These research results can undoubtedly serve as good reference for designing, fabricating and measuring novel strained silicon devices.