Research On The Scability And Fabrication Process Of Strained Stress Concentration MOSFET

Due to the high carrier mobility, adjustable band structure, compatible with the traditional process, obviously performance enhancement, strain Si technology attracts widespread attention. By shortening the device critical sizes in order to enhance the device performance has become more and more difficult. The scability of strained technique to enhance the nano-scaled device performance, further continuation of Moore’s law is of great significance. In nano-scaled devices, as the change of carrier transport mode, results in the change of stress enhance the device performance mechanism. Whether the strain technique is still effective need further study. At the same time as the device dimensions shrink, traditional strain technique faces such as stress relaxation, intensified three-dimensional effect makes it difficult to introduce stress into nano-scaled devices.In this thesis, the researches focused on scability of strained technique as the performance enhancement mechanism, stress enhancement methods of the nano-scaled strained MOSFETs are developed through theoretical analysis and experimental and simulation analysis. The main research work and the results are as follows:1. The stress resulted in device performance enhancement mechanism are studied based on the stress lead to the change of band structure, reduce of carrier scattering rates and effective mass, and short channel device carrier transport model, namely velocity overshoot and ballistic transport of nano-scaled devices. The study show that strain technique can effectively enhance the performance of the short channel devices, mainly achieved by decreasing the carrier effective mass and this would be the purpose of strain technique in nano-scaled devices. Meanwhile the challenges of traditional strain techniques faced in short channel devices are studied, and show that the scaled stress technique should integrate the advantage of virtual substrate technology, stress memorization technique(SMT) and CESL strain technology.2. Through analytical and finite element iteration solve on a elastic deformation flat plate structure with a hole in its central, the relationship between the stress distribution, stress concentration factor and the hole shape are achieved. The theory and Sentaurus simulation analysis are used to explore the channel stress distribution, stress enhances mechanics and device structure optimization of 15 nm to 350 nm channel length strained stress concentration devices. From simulation concluded that the channel stress increasing rapidly with the reducing of the top Si thickness and the hole filled materials Young’s modulus. The channel stress get over 50 MPa for oxide hole and 150 MPa for vacuum hole for the optimized stress concentration device structure with the top Si thickness reduced scaling compared with traditional CESL strain technique.3. Based on Sentaurus finite element solution for the gate length varied from 15 nm to 350 nm stress concentration MOSFETs, the devices electrical properties such as transfer and output characteristics, sub-threshold swing, DIBL, Vth, carrier mobility and electrical potential distribution are studied. The study show that the device performance enhance mainly attributed to the channel stress enhancement, followed by the low dielectric constant of hole materials. Over 12% driving currents enhancements are obtained compared with conventional strained devices when the channel length is greater than 20 nm. The driving currents enhancement rate increase with the decreases of the channel length and decrease after increasing first, and reach its peak at 65 nm Lg, increase by 18.4%. Compared with the traditional strain device, the strained stress concentration MOSFETs has good short channel effects as lower subthreshold swing and lower DIBL characteristics.4. In view of the optimized strained stress concentration device structure, the devices fabrication processes based on SOI technology and self-aligned selective etching of SiGe and Si was proposed. The high selective etch ratio of SiGe and Si are studied carefully through theoretical and experimental analysis, found that the HF,H2O2, concentrated CH3 COOH etching solution can obtained high etching ratio and good etching interface features. The device fabrication processes is suitable for long and short channel devices and have good compatibility with standard CMOS process at the same time.