Study On Stress Distribution And Electrical Properties Of Strained-Si MOS Devices By Simulation

With the continuous decreasing of the feature size of semiconductor device, the traditional scaling rule is encountering more and more physical challenges. Strained-Si technology has become one of the most promising approaches to further improve the performance of nano-scaled metal-oxide-semiconductor field effect transistors (MOSFETs). The improvement of carriers'mobility due to strain-induced energy band changes, as well as its compatibility with the current mainstream microelectronic process, makes the strained-Si technology very attractive and effective to improve the electrical properties of MOS devices. Actually, it has been widely acknowledged that this technology can continuously promote the development of integrated circuits in a long period while maintaining the advantages of planar silicon CMOS technology.It is very important to know the value and distribution of channel stress, and the effects of stress on device performance for designing, fabricating and applying strained-Si MOS devices. From the viewpoint of research time and experimental cost, studying these devices by simulation is worthy of more emphasis. Thus, in this paper, we use finite element analysis software ANSYS and Sentaurus TCAD tools to study the dependence of channel stress distribution on some important process parameters and the stress-induced electrical property changes in MOSFETs, respectively.When using ANSYS to perform channel stress analysis, we focus on the novel SiC S/D and the strained-Si on relaxed SiGe NMOS structure. Results indicate that the channel stress can be raised by either increasing the molar fraction of C/Ge, the recess depth and the elevation height of S/D, or reducing the thickness of the strained Si layer. Furthermore, the channel strain is more significantly influenced at shorter gate length. Besides, comparisons of simulation results and experimental data based on FFT (Fast Fourier Transform) analysis of HRTEM (High Resolution Transmission Electron Microscopy) image or CBED (Convergent Beam Electron Diffration) measurement verify the effectiveness and accuracy of finite element analysis results.The TCAD simulation results on strained-Si NMOS and PMOS with a gate length of 50 nm show that, high tensile stress SiN cap layer and SiGe S/D structure can be used to enhance electrical properties of NMOS and PMOS, respectively. The driven current and transconductance can been substantially improved. Stresses from multi-stressor structure can be superimposed in the channel region, leading to final improvement of electrical properties while without obvious degradation of sub-threshold characteristics. Both the trend and the values obtained from TCAD simulation are in good agreement with the experimentally measured transfering characteristics of MOS devices.Finally, TCAD simulation has been extended to small-scale circuit with a focus on the voltage transfering characteristics of CMOS inverter. Duo to the threshold voltage drift, the switch point voltage of strained-Si CMOS inverter shows a remarkable shift, and the noise margin is relatively smaller.Our simulation results can provide theoretical reference for nanoscale device design and optimization, for example, the compromised choice of C/Ge content, the effective control of elevation height and recess depth, and reasonable predictions to integration effect from multi-stressor structure. Undoubtedly, these results can serve as helpful guidance for fabrication and application of real strained-Si devices.