Stress Analysis Of Semiconductor Devices Based On Strained Si Technology

With the rapid development of nano-fabrication techniques, the feature size of transistors has advanced to the nanoscale. More and more physical and technology restrictions have appeared when continuing using CMOS scaling rule to raise their properties. In order to maintain the historic developing trend of integrated circuits predicted by Moore's Law, new materials, new structures and new physical properties compatible to current CMOS processing technologies have to be explored. Recently, strained Si technolohy has attracted wide attention as one of the major CMOS performance booster. For example, the hole mobility in PMOS and the electron mobility in NMOS can be significantly enhanced by introducing appropriate compressive and tensile channel stresses, respectively. The compressive channel stress in typical strained Si PMOS devices is usually produced by epitaxial SiGe souce/drain. The amount of strain can be controlled by the lattice mismatch between SiGe and Si. As a result, the hole mobility can be increased. For strained Si NMOS devices, the tensile channel stress is usually introduced by depositing a SiN cap layer with high intrinsic stress. The electron mobility is then controlled by the tensile strain. Thus, investigations of the dependence of stress and strain on the material and structural parameters in semiconductor nano-devices show great importance of science and practical applications.In most cases, however, the accurate measurement of local microscopic stress and strain in (ultra) deep sub-micron semiconductor structures must resort to complicated microstructure analysis methods. Since there is few simulation-based research on the strain field distribution in nanoscale strained Si devices, we decide to study the possibility of using the finite element analysis (FEA) and Sentaurus TCAD software to investigate the stress and strain in PMOS with typical SiGe source/drain structure and in NMOS with a SiN cap layer of high tension.The simulaton results obtained from ANSYS indicate that the calcaulted PMOS channel strain is in good agreement with the experimental data measured by the convergent beam eletron diffraction (CBED), verigying the feasibility and correctness of our simulation method. Further results indicate that the structure parameters of PMOS (for example, the gate length, the S/D etching depth, etc.) can be used to control the channel strain distribution in a certain range. On the other hand, the similar finite element simulation performed on NMOS with a high tensile SiN cap layer concludes that the channel strain is basically induced by the intrinsic stress in the SiN thin film, while the thermal stress showes relatively minor effect.Moreover, Sentaurus TCAD software is used to study uniaxial strained Si PMOS and NMOS devices of 50 nm gate length produced by Intel 90 nm processing technology. The first-stage simulation results are calibrated using the experimental data reported by Ghani et al. The channel compressive stress and the electrical properties of PMOS are found to be controlled by parameters such as the gate length and the Ge content, while the channel tensile stress and the electrical properties of NMOS are modulated by parameters such as the intrinsic stress, the SiN thickness and the gate height, which are consistent with the conclusions obtained from the previous part.