Three Dimensional Simulation Of Junctionless FinFET

The conventional metal-oxide-semiconductor field-effect transistors (MOSFETs)impose challenges, such as challenging fabrication process and deteriorated performances with the continuous miniaturization of device sizes at nanoscale regime, which is based on the Moore's Law. To overcome such problems, the use of FinFET, which is with a free-stand three-direction channel has been shown being able to enhance the function of gate on channel conductivity control and release the punch-through effect. However, very abrupt source and drain junctions requirement put challenges in doping profile techniques and thermal budget. Junctionless transistor (JLT), which does not have p-n junction in the source-channel-drain path, has better short-channel effects (SCEs) performance resulting better scalability, greatly simplified process flow, low thermal budgets after gate formation,and so on. As a result, junctionless (JL) FinFET is becoming the mainstream of next generation of nanoscale MOSFET.This dissertation focuses on three-dimension simulation of JL FinFET using Sentaurus TCAD, and further research of the influences of key parameters is also analyzed. It is found that the drain-induced barrier lowing (DIBL) decreases 50%, and subthreshold swing (SS)decreases 13% comparing with the inversion-mode FinFET. Thus, it has been demonstrated that JL FinFETs are less susceptible to SCEs. Moreover, it is found that the electrical characteristics can be improved by reducing the cross-sectional area, or increasing the gate length, or decreasing the gate oxide thickness. However, JLTs suffer from lesser drain current compared with inversion-mode MOSFETs due to high doping concentration in the channel region. At the same time, dual-material gate (DMG) devices and the use of high-k dielectric as a spacer can both bring an improvement in the drain current as well as the suppression of SCEs. The results show that the drain current of DMG JL FinFET increases significantly comparing with single-material gate (SMG) counterpart, and DIBL decreases 43%. It is acceptable that the SS increases a little. Finally the dual-material gate JL FinFET using high-k spacer dielectric (DMG-SP) is introduced. In the study of DMG-SP JL FinFET,it is observed that the new device brings an improvement in the drain current by more than one order of magnitude, and DIBL decreases 34% comparing with DMG counterpart.Therefore, DMG and DMG-SP JL FinFET devices offer impoved drain current and enhanced SCEs,and this dissertation provides the basis for research and application of JL FinFET in the nanoscale regime.