Research And Design Of Silicon-based Strained CMOS

From invention of the transistor to the emergence of ultra large scale integratedcircuits, Si-based semiconductor technology made a series of important breakthroughs,CMOS technology became the most widely used integrated circuit technology inmicroelectronics manufacture for its high integration, low power dissipation, and fastspeed. Currently, integated circuit with feature size of45nm has begun mass production,according to ITRS (International Technology Roadmap of Semiconductor) Roadmap’slatest forecast, CMOS process technology with feature size of21nm will be adapted formanufacture in2015.However, when the feature size enter deep micron region, a series of problemappeared to restrain the further improvement of device performance, especially for thedegeneration of carrier. Strained Si technology, which could significantly improve themobility of carrier, is regarded as an important method to extend the Moore Law.In this dissertation, research work is carried out in both theoretical andexperimental, which include theoretical analysis of strained Si/SiGe basic physicalproperties, physical model establishment of strained Si/SiGe MOS, and the physicalparameter design of strained Si/SiGe CMOS for further device manufacture. The mainresearch work and the results are listed as follow:1. Strained Si/SiGe CMOS is the elementary unit of high performance integratedcircuit. Three structures of Strained Si CMOS (Si/SiGe/Si Quantum Well(QW) channelCMOS，strained Si/SiGe CMOS and Si/SiGe/SiGe dual strain CMOS) are proposedbased on the mechanism of Strain enhance mobility and heterojunction band theory. ForSi/SiGe/Si CMOS, Quantum Well SiGe is regarded as channel of pMOS and Si caplayer is regarded as channel of nMOS; For strained Si/SiGe CMOS, both nMOS andpMOS treat Strained Si as their channel; For Si/SiGe/SiGe dual strain CMOS, strainedSiGe is made as the channel of pMOS, and strained Si layer on the surface treat aschannel of nMOS.2. In the device manufacturing process, threshold voltage is a very importantparameter. In this dissertation, the threshold voltage models of three kinds of nMOS andpMOS in CMOS with P+Poly SiGe are established, and the relationship betweenthreshold voltage and physical parameters is obtained by simulation. The validity of themodels is proved by experiments and device simulation software. According to thesimulation results, the way to restrain the parasitic channel existed in Si/SiGe/Si QW channel pMOS and Si/SiGe/SiGe dual strain pMOS are acquired. And I-V model forboth strained Si nMOS and that of pMOS are built which considered the velocityovershoot effect.3. The impact of Drain Induced Barrier Lowering(DIBL) effect on thresholdvoltage of strained Si/SiGe nMOS is analyzed by the charge share theory to be revised.This model is helpful for the design and manufacture of CMOS4. The strained material is produced by epitaxy. The test is carried out by the wayof XRD、TEM and Raman Spectra. The results show that the material had goodcrystallization and their density of defect is less than105cm-2which is good for devicefabrication.5. The paramters of strained Si/SiGe CMOS and Si/SiGe/Si QW well CMOS aredesigned based upon previous model and current process technology. Furthermore, theimpact of key process on device performance is also analyzed. The process for strainedSi CMOS and QW well CMOS are carried out. The tests of the devices show that theperformance of strained Si pMOS is improved and that of strained Si nMOS improvedby205%; the test of strained Si CMOS inverter shows that its high level is greater than4.9V and its low level is less than0.1V for the5V supply power.