Study On The Key Technology Of Three Dimensional CMOS Based On Strained Silicon

The lattice structure of strained silicon-based material, theory of tensile and compressive strain, basic physical properties of strained Silicon and strained Silicon Germanium, especially the strain-induced mobility enhancement are firstly analyzed based on its application on three dimensional integrated circuits (3D ICs) in this dissertation. The effects of strain on the band structure of Silicon and Silicon Germanium are studied, the bandgap models of strained Silicon and strained Silicon Germanium are presented, and the novel pn junction capacitance-voltage method is firstly used to measure the bandgap of strained Silicon Germanium. The mobility models of electron and hole in strained Silicon and strained Silicon Germanium that are available for Medici simulation are obtained by utilizing numeric fitting method, which are the theoretical fundamentals for design and optimization of three dimensional CMOS based on strained Silicon.Silicon wafer direct bonding and smart-cut technologies are analyzed and investigated, and then low temperature/high vacuum Silicon wafer direct bonding and smart-cut technologies is presented and used to fabricate Silicon on insulator (SOI) structure, finally, this SOI structure is successfully fabricated at 550℃and 2.1×10-2Pa. The bonding strength of this structure is 153.7Kgf/cm2, the total thickness variation and the defect density of the top monocrystalline silicon film are 8.5nm and 90cm-2, respectively. This method can yield the high quality monocrystalline silicon layer that could be available for the next active layers and form a good insulator layer between active layers in the fabrication of three dimensional CMOS based on strained Silicon, simultaneously avoiding the effection of the high-temperature process on the devices structure, material and performance of the active layers and effectively enhancing the bonding quality in low temperature/high vacuum annealing process.On the basis of SOI structure fabricated by low temperature/high vacuum Silicon wafer direct bonding and smart-cut technologies, a novel strained Silicon/strained Silicon Germanium three dimensional CMOS structure is presented, and its electrical characteristics are analyzed and simulated. The simulation results indicate that this CMOS structure has higher carrier mobility, drive current and transconductance, compared with bulk Silicon devices because strained Silicon and strained Silicon Germanium are used as channel for NMOS and PMOS, and this device has smaller parasitic capacitance, easiness to realize full dielectric isolation and higher integration, which could be widely used in high speed, low voltage and power circuits.A novel vertically stacked common gate strained Silicon/strained Silicon Germanium quantum well CMOS structure is presented and studied, tensile strained Silicon and compressive strained Silicon Germanium are used as quantum well channel for NMOS and PMOS in this structure, respectively, and carrier mobility can be enhanced. Simultaneously, p+poly Silicon Germanium is used as gate material in this structure, the adjustment and matching of threshold voltage in NMOS and PMOS are realized considering the continuous relationship between work function of p+poly Silicon Germanium and its Germanium mole fraction. Band structure, carrier sheet concentration, DC and AC characteristics of this CMOS are analyzed and simulated, and its validity is proved. The effects of several major parameters on NMOS and PMOS are discussed, and then optimal parameters of structure and electrical characteristics, such as, doping concentration ofδdoping layer, threshold voltage, transconductance and fT, etc. are obtained. Finally, the input-output characteristic of this CMOS inverter is simulated, and the simulation results indicate that this structure has correct logic function and good performance. This CMOS structure has such advantages as flexible design, high integration, compatible with bulk Silicon process and high frequency/high speed.