Design Of The Lower Power Arithmetic And Logical Unit

Arithmetic and Logical Unit (ALU) is one of the most important components in high-performance digital signal processor, which speed and power consumption have great effect on the performance of entire digital signal processor. Research work on the optimization methods of Full-Custom design and implement the high-performance ALU have important practical significance and value in a wide range of applications.The architecture of Arithmetic and logical Unit and the theory of core adder is studied in this thesis. In this thesis Bring forward and designed a sort of ALU that is fit for DSP Based on the architecture of DSP, the ALU function as two 16-bit ALU and 40-bit, the methods of combined Semi-Custom design optimization and Full-Custom design optimization adopted in thesis, which dramatically enhance the performance of ALU and reduced the power, the ALU is carried out at algorithm. Coding.logic structure, circuit and layout level. In a 0.25μm CMOS process and typic case, the results of logic synthesis and layout simulation show that the delay of critical pathe of the ALU can reach 0.932ns, power dissipation is 2.13mw, and layout area is 0.1012 mm~2 .which meets the requirements of the optimization. the ALU is succeed in X digital signal processorThis thesis mainly contributes to the following aspects.1 A sort of ALU is designed that is fit for DSP Based on the architecture of ALU and core adder,the ALU adopted parallel architecture that function as two 16-bit.2 The structure of computing adder's carry is improved when ALU at 40-bit mode, the latency of critical pathe is reduced .3 A clock-gating design optimization algorithm is proposed. it stop ALU clock when ALU at sleep mode .reduced creepage power that ALU at sleep mode. The optimization algorithm which is applied to the optimization of ALU, and achieves lower power.