Design And Verification Of High Speed Arithmetic And Logical Unit

A good design of Arithmetic and Logical Unit(ALU)is very important for high performance microprocessor in speed.On the based on arithmetic and research result in several years,the thesis designs a kind of practical 32-bit ALU in 0.18μm CMOS in X processor with the methodology of full custom,and in which it is optimized from algorithm level to layout level.This thesis mainly contributes to the following aspects:1.The core Adder is designed with the method of "lookahead inside and skip outside" in 32-b ALU(compatible with 8-b and 16-b).For purpose of parallel process, U and V pipelines are adopted in ALU.In 0.18μm process and typical case,the delay of critical path of complex U pipeline is 0.99ns,power dissipation is 72.9mW,and layout area is 0.091mm~2.The design achieves the goal of higher speed,lower power dissipation and smaller area.2.There are 26 general Registers designed in X processor including Read-Write control logic,the body of Register,clear and precharge logic.In 0.18μm process and typical case,the delay of critical path is lns,and layout area is 0.161mm~2.3.A kind of 64-b ALU is designed and its core Adder is realized by cascading Compound domino circuits.The Adder is structured with Han-Carlsontree.In 0.18μm process the delay of critical path in schematic circuit is 0.23n,power dissipation is 127.8mW.4.A kind of Dynamic circuit without Foot-Switch nMOS controlled by clock is proposed.When it resolves the correlation among clocks and between clock and data, the delay is decreased by about 21%in schematic simulation in foregoing 64-b Adder.Ultimately ALU can run precisely and stably in 300 MHz in practice and is succeed in X processor.