Research On Logic Parameter Extraction And Modeling Of Standard Cell And Memory Under Dsm Technology

With the development of micro-electronics technique, renewal period that the integrated circuit's design technology and manufacturing process is beginning more and more short, the circuit's logic parameter(delay, power , setup time, hold time etc.) must renew too with the technology continuously advanced. It asks for the large quantity manpower and material resources to extract logic parameter, also needs the longer time period and disadvantage in keeping up with the market's request. The designer of integrated circuit usually analyzes the performance of chip according to the logic parameter, therefore to extract logic parameter is very important. The current renewal work of logic parameter is mostly half auto and it should design stimulant wave by hand for the every kind of logic parameter, this not only takes a lot of time but also leads to mistake easy, ant it will influence the accuracy of logic parameter.We discuss systematically how to extract the logic parameter and modeling about standard cell and memory under deep submicron (DSM) technology on the foundation of research the domestic and international's related research result. We develop a tool of extraction logic parameter about standard cell, and proceed the in-depth research about memory logic parameter extraction and complete the works of stimulant wave and circuit reduction.On the analysis the function of standard cell and memory, take no account of the load of actual circuit and the actual input slew, bring up stimulant wave from logical .It not only avoids error from designing stimulant wave by hand, and but also reduces appreciably the extraction time.Because the scale of the memory circuit is very great, not completes extraction of logic parameter if don't reduces its circuit. A new method of circuit reduction for memory logic parameter is proposed. The method reduces the circuit by judging whether logic state of transistor alters or not while inputting specialized wave. Thestudies show it reduces the number of the transistor greatly and holds nicely functional performance and electrical characteristic of circuit. The precision of logic parameter extracted by this new method is very good and it cuts short greatly the extraction time. The experimental results show that it is efficiently. Final, we introduce the method of RC/RCL network reduction and applies to memory RC/RCL network reduction. A new method of active circuit extraction is proposed. The method takes advantage of structural property of memory and switch-level simulator to extract the active circuit accurately under a set of specialized stimulus wave.To study on deviation of sampling point under DSM technology, then algorithm of input slew driving is proposed to conquer the difference between input slew and actual slew, it increases nicely the precision of logic parameter. The parameter table compress algorithm can choose reasonably son parameter table to express the original parameter table.