| Since the beginning of the VLSI era, various technologies have been adopted for developing the design and characterization of analog circuits. For robust design, the influences of the process parameter variations have been considered over the circuit simulation. Previous studies in this field concentrated more on the physical dimensions such as the width, length, area and perimeter as well as the threshold voltage of the device.; The focus of this thesis was to characterize the performance of an analog IC standard cell library as well as optimize the simulation models. The circuits include n-channel metal-oxide semiconductor field-effect transistors (NMOSFETs), p-channel metal-oxide semiconductor field-effect transistors (PMOSFETs), poly resistors, current mirrors, comparators, bias generators, voltage references, op-amps, and voltage regulators. The spice model used for simulation was the Berkeley Simulator version 3 (BSIM3) model.; Tanner Research designed the majority of the standard cells evaluated. These cells were fabricated in the AMI 1.5-um CMOS process using the MOSIS service. The Integrated Circuits (ICs) have been developed using software from Tanner Research namely, the schematic editor (S-Edit), layout editor (L-Edit) and simulated using Tanner version of Spice (T-Spice). The simulations carried out on the circuits using the optimized model exhibited an overall performance improvement over the unoptimized model. Based on these simulations, numerous plots and tables are presented and the data was discussed in terms of the output tables are presented and the data was discussed in terms of the output characteristics. There was a noticeable improvement in the accuracy of 60.44% for the PMOSFET and 17.25% for the NMOSFET with the optimized model. The direct current (DC) fit using the optimized model over the unoptimized model showed an improvement of 2.17% (Voltage reference), 1--24% (Bias Generator), 2% (N-Current mirror), 5% (P-Current mirror), 11--30% (Analog Buffer) and 1.74% (Op-Amp). |
