The Design Of CMOS Low Phase Noise Voltage Controlled Ring Oscillator

In recent years, the voltage controlled ring oscillator based on CMOS has become a hotspot research, and high performance voltage controlled ring oscillator has been widely used in all aspects of life, and it has the tendency in replacing the inductance and capacitance type voltage controlled oscillator. However, the phase noise and frequency range of CMOS voltage controlled ring oscillator are limited, and need further research. So, this paper focuses on the analysis and study of the phase noise characteristics in voltage controlled ring oscillator. The main ideas are as follows:The main structure of the voltage controlled oscillator is made up of four differential delay cells; each of the delay cells use the symmetrical load, and has a linear characteristic of impedance. It improves the noise suppression ability and the tuning linearity, avoids the frequency mutation phenomenon, also it reduces the common mode interference. Based on the DC feedback concept, we complete the circuit of bias-replica module, and realize the regulation of the load impedance and leakage current at the same time. It ensures high spectral purity of the output waveform and constant amplitude, reduces the phase noise caused by the fluctuation of the oscillation amplitude. Also, the deviation because of temperature, humidity, process changes has reduced. Propose using the hysteresis comparator with internal positive feedback as the output stage. This method reduces the errors cased by the noise in judgments, ensures symmetrical rising and falling edges of the output waveform, improves phase noise suppression capability, and increases the load capacity. In the design, the frequency of voltage controlled ring oscillator is adjusted by dual control current, it is says that the leakage current of the delay cell is controlled via two kinds of current, finally achieve wide frequency adjustment.We completed the circuit design and per-simulation of the voltage controlled oscillator basing on the ideas. Also, we finished the circuit layout design and simulation verification, reduced the phase noise, increased the frequency regulation range, improved the frequency stability and reduced the chip area. The simulation results show that the phase noise at100kHz is about-95dBc/Hz, the frequency regulation range is about27MHz, the duty ratio of the output waveform is about52.8, and achieve the expected design requirements. We need to complete the layout design of the other modules, and do further improvement and optimization. More importantly, this design can be applied to the circuit of clock generation.