Research And Design Of Low-Power Cache In Embedded Systems

Power dissipation is the universal highlight of the embedded systems design during the recent years,which effects the applications and development of the embedded systems seriously. Cache plays the key role in decreasing the performance gap between the main memory and the microprocessor, which is also one of the main parts of the power elements.Therefore,the research on low-power cache for the low-power design of embedded systems is of important significance.The thesis studies the low-power cache design technology in architectural level. Firstly, we summarize and analyze the usual low power cache design techniques, and then propose two low-power cache models,which are the low-power unified cache model based on classification access scheme with valid-bit pre-decision (CAVPU Cache) and the low-power split cache model based on capacity co-allocation algorithm(CCAS Cache). The CAVPU cache owns the advantage of low power consumption and load self-regulation; The CCAS cache owns the advantage of low power consumption and load self-regulation and high bandwidth. The simulation results show that these low-power methods are valid. The main results of this thesis are as follows:1. A low-power unified cache model based on classification access scheme with valid-bit pre-decision is proposed. When accessing the traditional n way set-associative cache it should access all the ways at the same time. Thus it will result in increasing the energy consumption badly for that n-1 ways accessing is unnecessary. In this paper, a low-power classification access scheme with valid-bit pre-decision for unified cache is proposed based on the low-power classification access scheme. The low-power cache model can not only halt the cache blocks which are not matched but also halt the cache blocks that are not valid. The sub-block placement technology used in this low-power model can also decrease the miss dissipation. Mibench simulation results show that the low-power scheme can reduce the power consumption and improve the comprehensive performance effectively compared to the unified cache with classification access scheme.2. A low-power split cache model based on capacity co-allocation algorithm is proposed. Reconfigurable cache has a set of adjustable configurations, and the self-tuning algorithm for reconfigurable cache can monitor cache behavior, performance and modify its configurations dynamically based on the requirement of running program, which can minimize the power consumption and performance loss. A new capacity co-allocation algorithm is proposed in this paper based on the fact that different programs even different operational phases of a program usually need different sizes of the instruction cache and data cache and the need is usually imbalanced. This algorithm can co-adjust the configuration of level 1 cache dynamically based on the requirement of running program. Mibench simulation results indicate that the algorithm can not only lower the cache's energy consumption effectively compared to the previous works, which also can reduce the performance loss effectively caused by imbalanced allocation of capacity between the instruction cache and the data cache.