Research On Low-energy Cache And Dynamic Voltage Scaling In Architectural Level

With the lasting development of IC fabrication techniques, the density and speed of the chip increase rapidly, which makes the power density increase dramatically. Power, like performance, has become a first-class design constraint in computer architecture. In modern computer, the speed of CPU is much faster than that of memory. Cache can bridge the gap between high-speed processor and low-speed main memory. Cache is playing an important role on optimizing the performance of computer, but it consumes significant energy of CPU. Since the processor core and cache are the main sources of energy dissipation in computer, reducing their energy dissipation has significant means for the computer system, especially for the embedded system.The dissertation studies low energy design methods in structure level. The energy dissipation of processor and its cache are reduced by optimizing cache structure and dynamic voltage scaling algorithm. First, we summarize the usual low power cache design techniques, and classify the techniques into five types: module partitioning, way-predicting, attaching a small cache, partial tag comparison, and dynamic reconfigurable cache. We propose a partial tag comparison cache using valid-bit pre-decision, a split comparison cache using valid-bit decision, and a phase-based reconfigurable cache. Then based on analyzing existing dynamic voltage scaling technologies and their algorithms, a phase-based voltage scaling algorithm is presented. At last, a Phase-Based self-tuning algorithm for reconfigurable cache and processor is proposed via a combination of reconfigurable cache and dynamic voltage scaling. The simulation results show that these methods are valid.The main results of this dissertation are as following:1. A partial tag comparison cache using valid-bit pre-decision (PTC-V Cache) is proposed. Set-associative caches achieve low miss rates but result in significant energy dissipation. We propose a partial tag comparison cache using valid-bit pre-decision for set-associative cache. It could effectively decrease the energy dissipation of sense amplifier and data bit lines. The result showed that for the I-Cache, the PTC-V Cache eliminated on average 55% of the unnecessary energy consumption compared with a conventional Cache.2. A split comparison cache using valid-bit decision (SC-V Cache) is proposed. Based on the way-halting cache, SC-V Cache designs a valid-bit decision and split tag comparator. It could reduce the delay of tag comparison and the useless power consumption of accessing an invalid cache block. It achieves low energy dissipation and high performance. It significantly improves the average energy saving of the way-halting cache, especially for large size cache.3. A phase-based self-tuning algorithm (PBSTA) for reconfigurable cache is proposed. The algorithm uses state machine based on instruction working set signature for identify the change in program and making a decision to adjust cache's size, and uses state machine for governing cache and determining how to adjust cache's size in each phase. In contrast with previous works, the algorithm seeks not only to effectively lower the cache's energy consumption, but also reduce the performance loss due to unnecessary reconfigurations.4. A phase-based voltage scaling algorithm (PBVSA) is proposed. The algorithm uses state machine for identify the change in program and making a decision to change the processor's supply voltage and clock frequency, and sets processor's voltage and clock frequency by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time(β) in each phase. The results show PBVSA effectively saves the processor energy while meet the performance's need.5. A Phase-Based self-tuning algorithm for reconfigurable cache and voltage (CVPBSTA) is proposed. The algorithm combines PBSTA and PBVSA, which uses state machine for identify the change in program and making a decision to adjust cache's size and processor's supply voltage and clock frequency. In each phase, the algorithm successively adjusts cache's size and processor's voltage and clock frequency by respectively using the similar PBSTA and the similar PBVSA. The results show that CVPBSTA provides the better power savings while meet the performance's need.