Research Of High Performance Low Power Cache Based On The Method Of Way Halting

Cache can improve the computer performance by bridging gap the between high-speed processor and low-speed main memory. But Cache dissipates a large amount of energy of CPU. High-end processor chips are becoming very high in temperature, calling for lower power solutions. Embedded processor chips often have little cooling capability and need low energy technology to prolong battery-powered time, so the designer must consider many factors such as performance, energy consumption.First, we studied the power dissipation of Cache in terms of computer architecture by analyzing optimization method for power dissipation on system level. Combining the split comparator with modified way halting Cache model which is able to cut down inside activities during the Cache access procedure, a new kind of Cache model named split comparison Cache has been brought forward. It is able to raise system performance notably while economizing energy consumption. With the help of the valid-bit pre-decision which is based on the split comparison Cache, we proposed a split comparison Cache using valid-bit pre-decision. It contributes eliminating energy consumption during accessing to an invalid block, thereby achieving high-performance and low-power consumption at the same time.Second, we analyzed Simplescalar and Wattch simulator on computer architecture level. Simplescalar is an architectural simulator, supporting the out-of-order pipelined processor and dynamic scheduling multi-level memory structure; Wattch has more function like calculating Cache energy consumption and accessing time on the basis of Simplescalar. In the initial stage of system structure designing, we are able to ascertain the Cache organization, to achieve the desirable performance and meet the energy consumption requirement.Finally, we tested the validity of both split comparison Cache and split comparison Cache using valid-bit pre-decision by experimentation. Simulation results indicate that the split comparison Cache using valid-bit pre-decision is able to save on 8% of the access time and 60% of the energy of a conventional four-way set-associative cache on average.