Research And Design On High Speed Full-parallel Analog-to-Digital Converter

With the rapid development of computer, communications and multimedia technology, the digitization process of high-tech fields is speeding up, which proposes a higher demand to Analog-to-Digital (referred to as ADC or A/D). In order to adapt to these requirements, currently, the A/D is moving toward high-speed, high-resolution and low-power. Especially in the fields of medical image, radar, oscilloscopes, read channel of hard disk drive, wireless communications, it requires higher and higher speed to ADC.This paper is mainly to research and design the ADC of high speed, appropriate resolution based on CMOS technology. Research and conclusion are as follows:(1) Propose a new 4bit full-parallel analog-to-digital circuit, and its maximum sampling rate is up to 5GHz. The performance of the ADC is mainly to improve and design from the following aspects: The ADC adopts the full parallel structure of non-sample/hold circuit, its sample/hold function is completed by the comparator; The ADC circuits are controled by a single clock, so its comparator and decoder circuits are pipelining; Using low-swing input and output signals, fully differential input and output way and the low-swing clock control, which leads to increase conversion speed and lowers signal to noise ratio of the ADC; Comparator circuit adopts inductance technology and multi-stage cascade mode to improve the conversion speed of comparator and to reduce the error rate; Decoder circuit makes use of decoding method based on current mode logic gate circuit: firstly, the thermometer code are converted into Green code, and then it will be converted into binary code, which further improve the conversion speed of decoder and reduces the ADC's error rate.(2) Propose a new 6bit full-parallel analog-to-digital circuit using interpolation technology, and its maximum sampling rate is up to 4GHz. New interpolation mode is proposed: Resistance and active interpolation are cascaded in interpolation mode, which makes the interpolation factor up to 8. So it reduces the number of the interpolation resistances and amplifiers, moreover, it lowers the requirements to the linear range of the interpolation amplifier.Besides, the paper does simulation to the two ADCs. Simulation results show that the measured static INL and DNL errors of the 4 bit ADC are 0.255LSB and 0.171LSB respectively, and its measured ENOB with a 100MHz input is 3.74bits at 5GS/s and disspates 65mW power consumption. And the measured static INL and DNL errors of the 6 bit ADC are 0.243LSB and 0.124LSB respectively, and its measured ENOB with a 100MHz input is 5.02bits at 4GS/s and disspates 220mW power consumption.