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Hardware Software Partitioning Method Based On Multimedia Applications

Posted on:2006-09-08Degree:DoctorType:Dissertation
Country:ChinaCandidate:Y P PengFull Text:PDF
GTID:1118360212482186Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Multimedia techniques have been used in handhold devices such as mobile,PMC and MP3 player driven by market. From simple FM to MP3 and MIDI player, more multimedia applications have been asked to integrate into the handhold devices with low computability. For fulfilling the requirement,SoC with multimedia support has been designed and used to improve the system power of multimedia.To design the type of SoC, hardware-software partitioning method which divides the system into many portions with different implementation has been used. And hardware can cooperate with software to meet system constraints with low cost. In the process, it is the most key step that effective hardware- software partitioning method facing to multimedia applications.The paper does research on hardware-software partitioning involving applications with data flow such as MP3 and MPEG4. Single CPU and ASIC for the executive components and single-level bus network for communication make up of the target architecture before hardware software partitioning. Partitioning granularity and binary mapping are different between our partitioning methodology and traditional partitioning methodology.Traditional hardware software partitioning only considers fixed partitioning granularity or binary mapping.In the contrast with traditional methodology,our methodology considers flexible partitioning granularity and extended mapping at the same time.Genetic Algorithm constructs complete running frame, and other processes are running on the frame.Double-genes code and selection, crossover and mutation ge-netical operations have been designed and used to solve the hardware software partitioning.Especially, invalid solutions could be repaired by repairing operation.For verifying the efficiency of the methodology presented by the paper,random graph test environment has been built by TGFF of Princeton and parser in PERL developed by the paper.Three types of experiment with random test vectors have been made to verify the efficiency of flexible granularity and extended mapping.Experiment for comparing to rajesh's method has been also made. The compared results show the method presented by the paper is effective and high efficiency.The paper has built up the complete processing including float point convert to fixed point, parameter extraction and annotation, hardware software partitioning algorithm, performance estimated by tasks scheduling and virtual prototype system. Multimedia accelerator in the Project-Zhongzhi 805 plus has also verified the effectiveness and efficiency of the method and improved the insufficiency with only random test vector.In the end, the paper gives the outline and future work.Creative works in the paper have been listed as follows: Firstly,model has been presented which integrated flexible granularity and extended mapping into hardware software partitioning. Secondly,Double-genes coding and selection, crossover and mutation genetical operations have been designed and used to solve the hardware software partitioning in the genetic algorithm running process based on the model.Thirdly,complete processing for hardware software partitioning has been built.Rapid performance evaluator based on critical path scheduling is the inner loop.Meanwhile,performance evaluator based on virtual prototype in SYSTEMC is the outer loop.
Keywords/Search Tags:System-on-a-chip, Hardware-software partitioning, Virtual prototype
PDF Full Text Request
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