Research And Application Of Dynamic Reconfigurable System-on-Chip Scheduling Technology

The dynamic reconfigurable System-on-Chip integrates a Central Processing Unit(CPU)and Field-Programmable Gate Array(FPGA)with dynamic partial reconfigurable features.It is an important heterogeneous system;the system has big advantage in processing,size,weight and power consumption,so it has been widely used.Dynamic partial reconfigurability means that the system can dynamically update the functionality of some hardware units at runtime without interrupting other tasks that are being executed.But full reconfiguration requires interrupting the task being carried out and reconfiguring all of the hardware elements of the FPGA.However,this runtime dynamic partial reconfigurability also brings additional reconfiguration delays while effectively improving the flexibility and resource utilization of System-on-Chip.The reconfiguration delay is positively related to the number of reconfiguration and the size of the reconfigurable configuration file.Therefore,only the reasonable hardware and software partitioning of the application can maximize the advantages of the dynamic partial reconfigurable features of the system.The purpose of hardware and software partitioning,i.e.,scheduling technology,is to obtain a scheduling scheme with the shortest scheduling length,which includes mapping,timing,and sorting of tasks.T his problem can be categorized as a combinatorial optimization problem,which can usually be solved using a mixed integer linear programming or stochastic optimization algorithm.The results of the solution can provide solutions for the design of dynamic partial reconfigurable System-on-Chip,especially for strict real-time demanding applications such as aerospace,industrial control,cloud computing and 5G.Based on the above background,we have carried out a series of research on the dynamic partial reconfigurable System-onChip scheduling technology and its application,mainly completing the following works:(1)Stochastic optimization algorithm and consturction of MILP or ILP models are often used to solve hardware and software partitioning problems,but stochastic optimization algorithms are difficult to converge and its results are easy to fall into local optimum.Therefore,this paper proposes a simple and efficient MILP model based on the software and hardware partitioning of dynamic partial reconfigurable System-on-Chip.Firstly,the application is divided into sub-tasks according to a certain granularity and pre-clustering processing is performed on the task set.Secondly,the software and hardware partitioning problem is completely mathematicalized and the complexity of the model is reduced by reducing the redundant variables and constraint equations existing in the traditional model,thus shortening the solution time of the problem.(2)Cluster-based hardware and software partitioning needs to plan tasks before the deployment of application.The results of clustering constrain the task-to-processor mapping.It is mainly used for task resource occupancy,reconfigurable area quantity and size are pre-known,also where the resources of the systems are limited.In order to make the scheduling results suitable for more common scenarios,this paper proposes a new MILP model,which removed the assumption of clustering.On the premise of solving the same application scheduling problem,the experimental results of the two models are analyzed and the performance of them is compared.(3)The ultimate goal of the hardware and software partitioning algorithm is to provide a reasonable deployment solution for the dynamic partial reconfigurable design of applications.The experiment carried by the computer simulation can only explain the effectiveness of the algorithm,and can not verify the practicability of the algorithm in engineering.In order to verify the practicability of the hardware and software partitioning algorithm,this paper designs a dynamic partial reconfigurable framework which based on IP(Intelligent Property)kernel.Based on the framework,the reconfiguration between tasks can be quickly realized,which effectively reduces the engineering verification period and difficulty of the algorithm.(4)Based on the above work,this paper selects the QPSK(Quadrature Phase Shift Keying)receiver which commonly used in 5G and satellite communications to verify the practicability of the proposed dynamic partial reconfigurable scheduling algorithm.Firstly,we perform DAG(Directed Acyclic Graph)modeling,hardware and software partitioning for QPSK receiver according to the construction process of noncluster MILP model proposed in(2);secondly,based on the result of the division,the hardware implementation of the application is implemented,and the tasks deployed on the hardware are encapsulated into corresponding IP cores;finally,based on the framework p roposed in(3),we verify the performance of the partitioning results and analyze the benefits brought by the dynamic partial reconfigurable feature.