A Design Of VCO In Charge-Pump Phase Locked Loop

With the development of the SoC (system on chip) technology, as a system clock unit, PLL (Phase-locked loop) plays an important part in a SOC. Because of controllable frequency, CMOS voltage-controlled oscillator (VCO) has become the mainstream of the internal oscillator in the PLL. In this paper, with the process of SMIC 0.35um, a larger frequency range and low noise differential ring VCO is designed for a PLL. And the PLL can be designed for high speed DAC and ADC circuits.This paper first introduces the basic principle of the oscillator, and then focuses on analyzing the structure of ring oscillator. Based on the performance of the oscillator, six levels ring VCO is selected. And then a complete design is given including circuit and layout design. In order to reduce IC design and simulation time, Verilog_A is utilized to model the VCO, which can be used to guide the following circuits design. In this paper, circuit design mainly includes bias circuit, ring oscillator circuits and shaping circuit unit. In order to reduce the lock time of PLL, the frequency limiting circuit is introduced to this VCO. In order to provide a full swing of frequency source, a shaping circuit is introduced in this VCO. Layout design of mixed signal circuits is an important aspect, in order to reduce the noise and interference of layout design, matching,symmetrical and shielding interference are utilized.Finally the former circuits simulation and post-simulation results are given by HSPICE,Spectre and mixed signal simulation tool-Nanosim. The output frequency range of VCO is 96MHz—400MHz, and when the output frequency of VCO is 400MHz, the phase noise is -104dBc/Hz@1MHz. The PLL based on the VCO in this paper is used in a high speed DAC, after MPW manufacture and testing the results achieve the desired objectives.