Design Of Widely Tunable, Low Phase-Noise, Low Power Dissipation LC VCO

As the explosive development in wireless communications, the research of the radio frequency (RF) electric circuit has caused much more attention. And the circuit with low cost and low power dissipation also attracts more and more integrated circuit (IC) designers. Particularly with the on-chip passive elements such as spiral inductors and varactors appeared, it makes on-chip integrated circuit which has some complicated functions possible such as on-chip implementation of LC-tank voltage-controlled oscillators (VCOs).This thesis is mainly based on the on-chip implementation of LC-tank voltage-controlled oscillators which are mentioned above. In this thesis, we have discussed the principle and realizations of RF LC voltage controlled oscillators. And we have analyzed the main factors, such as phase noise, power dissipation and tuning scope, which affects the characters of LC voltage controlled oscillators. Based on the study of linear time invariant(LTI) model and linear time varying(LTV) model,this paper discusses the underlying physics of LC-VCO in detal.With the noise model presented,this thesis obtains the expressions of phase noise in different frequency region.The general process of LC-VCO's design and optimization is summarized.The thesis analyzes the model of on-chip spiral inductors and the realization of varactors.After that,a optimized spiral inductor model was obtained with the help of the ASITIC,first analyzed these three main parameters are process parameters, including: metal resistivity, substrate resistivity and the distance between metal and substrate ,then analyzed the geometrical parameters, including: shape, compactness, spacing, metal width and turns. in this work, we mainly pay attention to optimizing the performance of the VCO's phase noise,tuning rang and power dissipation. In this design, we use switched tuning and tail current shaping-filtering technology besides choosing proper circuit structure and parameter of the devices to realize a better performance of phase noise,tuning rang and power dissipation.circuit was designed in TSMC 0.18um CMOS process, and simulated by the SpectreRF in Cadence under supply voltage of 1.8V. The center frequency of the VCO was 1.8G. The output frequency ranged from 1.55G to 2.08G, Phase noise was -121dBc/Hz at an offset of 600kHz. The static current of the circuit was 1.39mA.The static dissipation was 2.5mW.